Maximum transition run (MTR) codes limit the number of consecutive transitions in a bit sequence. For example, an MTR-3 code enforces a constraint where the maximum number of consecutive transitions is 3. A bit sequence of “10101” has 4 consecutive transitions and so (in one example) an MTR-3 modulator modifies the bit sequence to be “10111” (which reduces the number of consecutive transitions to 2).
Some MTR modulators input a bit sequence of length k and output a bit sequence of length n where n>k. This may require a clock that is n/k times faster than if MTR were not used. Making a semiconductor operate at a faster clock frequency is undesirable because it increases power consumption and/or increases the difficulty of timing closure (one of the steps in designing a semiconductor). Another issue is that when MTR codes are used in combination with error correction codes (ECC), such as Reed-Solomon codes and low-density parity-check (LDPC) codes, the MTR code may introduce error propagation into the system. New modulation codes which do not have these issues would be desirable.